1. Field of the Invention
This invention relates to a TDMA communication apparatus with intermittent receiving, particularly to a receiving apparatus with intermittent receiving.
2. Description of the Prior Art
A receiving apparatus for receiving a TDMA (Time Division Multiple Access) communication signal and for receiving a reception control channel to perform intermittent receiving operation to save a power consumption during the standby condition is known. In such a prior art receiving apparatus, it is necessary to keep TDMA synchronizing to receive the reception control channel, so that there was a limitation in saving power in the clock circuit.
The aim of the present invention is to provide a superior receiving apparatus with intermittent receiving.
According to the present invention there is provided a first receiving apparatus with intermittent receiving includes a receiving circuit responsive to a system clock signal for receiving a TDMA radio wave signal including frequency reference signal, a TDMA synchronizing signal, a broadcast signal, a reception control signal, and a communication signal; an equalizing circuit responsive to the system clock signal for equalizing the TDMA radio wave signal and outputting an equalized signal; a frequency detection circuit responsive to the equalized signal for detecting a frequency and a phase of the frequency reference signal in the equalized signal; a correlation detection circuit responsive to the equalized signal for detecting a correlation between the TDMA synchronizing signal in the equalized signal and a predetermined data pattern representing TDMA timing; a clock generation circuit including supply power control circuit, a d/a converter supplied with a supply power through the power supply control circuit and a voltage controlled oscillator for generating the system clock signal of which frequency and phase are controlled in accordance with frequency control data when the d/a converter supplied with the supply power and generating the system clock signal at a predetermined self-oscillation frequency when the d/a converter is not supplied with the supply power; a TDMA timing signal generation circuit for generating a TDMA timing signal in accordance with timing control data; a timer circuit for generating a timing signal; a microprocessor supplied with the system clock signal, including a memory for storing the frequency control data and data of the predetermined frequency, in a continuous receiving receiving mode, the microprocessor generating the frequency control data to control the frequency and phase of the system clock signal in accordance with the detected frequency and phase to establish a system clock synchronizing condition with the frequency reference signal, generating the timing control data in accordance with the detected correlation to establish a TDMA synchronizing condition with the TDMA synchronizing signal, in an intermittent reception mode, the microprocessor detecting data of an intermittent operation interval in the broadcast signal, storing the frequency control data, stopping supplying the supply power to the d/a converter using the supply power control circuit, setting and starting the timer circuit to generate the timing signal at a timing a predetermined period before the intermittent operation interval expires, and in response to the timing signal, the microprocessor supplying the supply power to the d/a converter using the power supply control circuit, reading the frequency data from the memory, supplying the read frequency control data to the d/a converter, calculating the timing control data from the intermittent operation interval data and data of the predetermined self-oscillation frequency to compensate the timing control data to establish the TDMA synchronizing condition again just before the intermittent operation interval expires to receive the reception control signal and the communication signal.
In the first receiving apparatus, the microprocessor controls the equalizing circuit to receive the communication signal in accordance with data in the reception control signal.
According to the present invention there is also provided a second receiving apparatus includes: a receiving circuit responsive to a system clock signal for receiving a TDMA radio wave signal including frequency reference signal, a TDMA synchronizing signal, and a broadcast signal, reception control signal, and a communication signal; an equalizing circuit responsive to the system clock signal for equalizing the TDMA radio wave signal and outputting an equalized signal; a frequency detection circuit responsive to the equalized signal for detecting a frequency and a phase of the frequency reference signal in the equalized signal; a correlation detection circuit responsive to the equalized signal for detecting a correlation between the TDMA synchronizing signal in the equalized signal and a predetermined data pattern representing TDMA timing; a clock generation circuit including supply power control circuit, a d/a converter supplied with a supply power through the power supply control circuit and a voltage controlled oscillator for generating the system clock of which frequency and phase are controlled in accordance with frequency control data when the d/a converter supplied with the supply power and generating the system clock at a predetermined self-oscillation frequency when the d/a converter is not supplied with the supply power; a TDMA timing signal generation circuit for generating a TDMA timing signal in accordance with timing control data; a timer circuit for generating a timing signal at a timing in accordance with timer control signal; a microprocessor supplied with the system clock, including a memory for storing the frequency control data and data of the predetermined frequency, in a continuous reception mode, the microprocessor generating the frequency control data to control the frequency and phase of the system clock in accordance with the detected frequency and phase to establish a system clock synchronizing condition with the frequency reference signal, generating the timing control data in accordance with the detected correlation to establish a TDMA synchronizing condition with the TDMA synchronizing signal, in an intermittent reception mode, the microprocessor detecting data of an intermittent operation interval in the broadcast signal, storing the frequency control data, stopping supplying the supply power to the d/a converter using the supply power control circuit, setting and starting the timer circuit to generate the timing signal at a timing a predetermined period before the detected intermittent operation interval expires, and in response to the timing signal, supplying the supply power to the d/a converter and reading the frequency data from the memory and supplying the read frequency control data to the d/a converter, detecting the correlation using the correlation detection circuit to compensate the timing control data to establish the TDMA synchronizing condition again Just before the intermittent operation interval expires to receive the reception control signal and the communication signal.
According to the present invention there is further provided a third receiving apparatus including: a receiving circuit responsive to a system clock signal for receiving a TDMA radio wave signal including frequency reference signal, a TDMA synchronizing signal, and a broadcast signal, reception control signal, and a communication signal; an equalizing circuit responsive to the system clock signal for equalizing the TDMA radio wave signal and outputting an equalized signal; a frequency detection circuit responsive to the equalized signal for detecting a frequency and a phase of the frequency reference signal in the equalized signal; a correlation detection circuit responsive to the equalized signal for detecting a correlation between the TDMA synchronizing signal in the equalized signal and a predetermined data pattern representing TDMA timing; a clock generation circuit including supply power control circuit, a d/a converter supplied with a supply power through the power supply control circuit and a voltage controlled oscillator for generating the system clock of which frequency and phase are controlled in accordance with frequency control data when the d/a converter supplied with the supply power and generating the system clock at a predetermined self-oscillation frequency when the d/a converter is not supplied with the supply power; a TDMA timing signal generation circuit for generating a TDMA timing signal in accordance with timing control data; a timer circuit for generating a timing signal at a timing in accordance with timer control signal; a microprocessor supplied with the system clock, including a memory for storing the frequency control data and data of the predetermined frequency, in a continuous reception mode, the microprocessor generating the frequency control data to control the frequency and phase of the system clock in accordance with the first detected frequency and phase to establish a system clock synchronizing condition with the frequency reference signal, generating the timing control data in accordance with the detected correlation to establish a TDMA synchronizing condition with the TDMA synchronizing signal, in an intermittent reception mode, the microprocessor detecting data of an intermittent operation interval in the broadcast signal, storing the frequency control data, stopping supplying the supply power to the d/a converter using the supply power control circuit, setting and starting the timer circuit to generate the timing signal at a timing a predetermined period before the intermittent operation interval expires, and in response to the timing signal, the microprocessor supplying the supply power to the d/a converter, reading the frequency data from the memory, supplying the read frequency control data to the d/a converter, operating the frequency detection circuit to detect a second detected frequency of the frequency reference signal, generating the frequency control data in accordance with the second detected frequency, calculating the timing control data from the data of intermittent operation interval and data of the predetermined self-oscillation frequency to compensate the timing control data to establish the TDMA synchronizing condition again Just before the detected intermittent operation interval expires to receive the reception control signal and the communication signal.